1. Field of the Invention
The present invention generally relates to the manufacture of transistors for integrated circuits and, more particularly, to the production of complementary pairs of field effect transistors of enhanced performance at extremely small scale.
2. Description of the Prior Art
Performance and economic factors of integrated circuit design and manufacture have caused the scale of elements (e.g. transistors, capacitors and the like) of integrated circuits to be drastically reduced in size and increased in proximity on a chip. That is, increased integration density and proximity of elements reduces the signal propagation path length and reduces signal propagation time and susceptibility to noise and increases possible clock rates while the reduction in element size necessary for increased integration density increases the ratio of functionality which can be provided on a chip to the costs of production (e.g. wafer/chip area and process materials) per chip and, potentially, the cost of devices containing the chips by reducing the number of inter-chip and inter-board connections required.
In response, many improvements in transistor design have been made to maintain suitable levels of performance of these elements, for example, lightly doped drain (LDD) structures (now generally referred to as extension implants since heavier doping levels have been required in current minimum feature size regimes), halo implants and graded impurity profiles have been employed to counteract short channel and punch-through effects and the like, particularly in field effect transistors (FETs) which have become the active device of choice for all but the highest frequency devices. Reduction in device scale has also required operation at reduced voltages to maintain adequate performance without device damage even though operating margins may be reduced.
Thin silicon channel Si devices are becoming a promising option to continue SOI CMOS scaling. It has the advantage of sharper sub-threshold slope, high carrier mobility (because the device is operated at a lower effective field), and better short channel control. Although these attributes are highly desirable, thin silicon channel Si devices have significant disadvantages that could hinder further SOI CMOS scaling. The primary disadvantage is that as the SOI film is thinned, the series resistance increases.
In some prior art thin Si channel devices, the extensions are implanted prior to raised source-drain (RSD) formation. RSD is used to reduce series resistance by increasing the Si thickness outside the channel region. This causes at least two problems. The first problem is that since the pFET extension requires a fairly thick offset spacer, a high resistance region exists under the spacer. The second problem is that since the extension implants are performed prior to the RSD process, the dopants are subjected to the significant thermal budget of the RSD process. This can cause unwanted diffusion of the dopants. In addition, the incubation time (e.g. anneal time) is different for p and n type Si which leads to substantially different RSD thickness for pFET and nFET. Also, the surface concentration of the dopants must be uniform across the wafer as well as from wafer to wafer, which is a major challenge, if the RSD process is to be manufacturable.
In another prior art thin Si channel device, a disposable spacer is used. A wide disposable spacer is used to grow the RSD. Next the deep source and drain implants are done. After this, the spacer is removed, and the extensions are implanted. Although the disposable spacer scheme overcomes the problem of subjecting the extensions to the RSD thermal budget, this process does not overcome the problem of the high-resistance region outside the RSD layer. Accordingly, it is clear that a need exists for a method to overcome the high resistance problem as well as the thermal budget problem.
Typically a trade-off exists between short channel effect control and high current. Specifically, an optimal performance nFET 100 is achieved using a small spacer 121a as shown in FIG. 1g while the optimal pFET 200 has a much larger spacer 221b as shown in FIG. 1h. This is due to the fact that the diffusivity of boron is significantly higher than that of arsenic: the materials used in the pFET 200 and nFET 100 gate areas 122, 222, source and drain regions 128, 228, and extensions 125, 225 respectively. The halo regions 124, 224, however, are boron in the nFET 100 and arsenic in the pFET 200. As shown in FIG. 1g, the boron source and drain regions 228 and extensions 224 of the pFET 200 are diffused greatly during the anneal process thereby creating the short channel effect in the pFET unless a thick spacer is used. The nFET 100 is largely unaffected by the anneal, with the exception of the halo regions 124 diffusing slightly. The nFET 100 performs very well when manufactured using thin offset spacers 121a. FIG. 1h shows how performing the manufacturing process using thick spacers 121b, 221b improves the pFET 200 performance by avoiding the short channel effect, as the source and drain regions 228 are implanted further out from the channel. When annealed, the boron implants 228, 225 diffuse to a beneficial placement. However, the arsenic source and drain regions 128 of the nFET 100 do not adequately diffuse yielding poor performance and a high level of resistance under the thick spacer. Thus, a need exists for an ultra-thin Si MOSFET having a smaller offset for nFET compared to pFET on the same wafer. Such a configuration, however, has not been practical due to the increase of process steps to form spacers of different thicknesses.